An Improved Power Efficient Clock Pulsed D Flip-flop Using Transmission Gate

Updata:01-01-1970

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DOI: https://doi.org/10.30564/jeis.v5i1.5574

Abstract:

Recent digital applications will require highly efficient and high-speed gadgets and it is related to the minimum delay and power consumption. The proposed work deals with a low-power clock pulsed data flip-flop (D flip-flop) using a transmission gate. To accomplish a power-efficient pulsed D flip-flop, clock gating is proposed. The gated clock reduces the unnecessary switching of the transistors in the circuit and thus reduces the dynamic power consumption. The clock gating approach is employed by using an AND gate to disrupt the clock input to the circuit as per the control signal called Enable. Due to this process, the clock gets turned off to reduce power consumption when there is no change in the output. The proposed transmission gate-based pulsed D flip-flop’s performance with clock gating and without clock gating circuit is analyzed. The proposed pulsed D flip-flop power consumption is 1.586 µw less than the without clock gated flip-flop. Also, the authors have designed a 3-bit serial-in and parallel-out shift register using the proposed D flip-flop and analyzed the performance. Tanner Electronic Design Automation tool is used to simulate all the circuits with 45 nm technology.

References:

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