Flip Chip Die-to-Wafer Bonding Review: Gaps to High Volume Manufacturing

Updata:01-01-1970

Source:
By:Mario Di Cino, Feng Li

DOI: https://doi.org/10.30564/ssid.v4i1.4474

Abstract:

Flip chip die-to-wafer bonding faces challenges for industry adoption due to a variety of technical gaps or process integration factors that are not fully developed to high volume manufacturing (HVM) maturity. In this paper,flip-chip and wire bonding are compared, then flip-chip bonding techniques are compared to examine advantages for scaling and speed. Specific recent 3-year trends in flip-chip die-to-wafer bonding are reviewed to address the key gaps and challenges to HVM adoption. Finally, some thoughts on the care needed by the packaging technology for successful HVM introduction are reviewed.

References:

[1] Tummala, R.R., 2001. Fundamentals of Microsystems Packaging. 1st ed, McGraw-Hill Education. pp.34. [2] Elenius, P., Levine, L., July/August 2000. Comparing Flip-Chip and Wire-Bond Interconnection Technologies. Chip Scale Review. pp. 81-87. [3] Li, M., Xu, H., Lee, S.R., et al., May 2008. Eddy Current Induced Heating for the Solder Reflow of Area Array Packages. IEEE Transactions on Advanced Packaging. 31(2), 399-403.DOI: https://doi.org/10.1109/TADVP.2008.923385 [4] Ohyama, M., Mizuno, J., Shoji, S., et al., 2014.Fine-pitch hybrid bonding with Cu/Sn microbumps and adhesive for high density 3D integration. 2014 International Conference on Electronics Packaging (ICEP). pp. 604-607. DOI: https://doi.org/10.1109/ICEP.2014.6826751 [5] https://ieeexplore.ieee.org/search/searchresult.jsp?queryText=flip%20chip%20die%20to%20wafer%20bonding&highlight=true&returnFacets=ALL&returnType=SEARCH&matchPubs=true&ranges=2006_2021_Year. (Accesssed 8 December 2021) [6] https://ieeexplore.ieee.org/search/searchresult.jsp?queryText=flip%20chip%20die%20to%20wafer%20bonding&highlight=true&returnType=-SEARCH&matchPubs=true&ranges=2006_2021_Year&returnFacets=ALL&searchWithin=wire%20bond. (Accesssed 8 December 2021). [7] Podpod, A., Phommahaxay, A., Bex, P., et al., 2019.Novel Temporary Bonding and Debonding Solutions Enabling an Ultrahigh Interonnect Density Fo-Wlp Structure Assembly with Quasi-Zero Die Shift. 2019 International Wafer Level Packaging Conference (IWLPC). pp. 1-6.DOI: https://doi.org/10.23919/IWLPC.2019.8914144 [8] Wen, S., Goodelle, J., Moua, V., et al., 2021. Cu Pillar Bump Design Parameters for Flip Chip Integration. 2021 IEEE 71st Electronic Components and Technology Conference (ECTC). pp. 211-216.DOI: https://doi.org/10.1109/ECTC32696.2021.00044 [9] Souriau, J.C., Castagné, L., Ladner, C., et al., 2020.Flexible Fan-Out Wafer Level Packaging of Ultra-Thin Dies. 2020 IEEE 70th Electronic Components and Technology Conference (ECTC). pp.37-41.DOI: https://doi.org/10.1109/ECTC32862.2020.00019 [10] Gao, G., Workman, T., Uzoh, C., et al., 2020. Die to Wafer Stacking with Low Temperature Hybrid Bonding. 2020 IEEE 70th Electronic Components and Technology Conference (ECTC). pp. 589-594.DOI: https://doi.org/10.1109/ECTC32862.2020.00098 [11] Gao, G., Mrozek, P., Workman, T., et al., 2019. Chip to Wafer Hybrid Bonding with Cu Interconnect: High Volume Manufacturing Process Compatibility Study. 2019 International Wafer Level Packaging Conference (IWLPC). pp. 1-9. DOI: https://doi.org/10.23919/IWLPC.2019.8913877 [12] Inoue, F., Derakhshandeh, J., Gerets, C., et al., 2021.Cobalt-Tin Intermetallic Compounds as Alternative Surface Finish for Low Temperature Die-to-Wafer Solder Stacking. 2021 International Conference on Electronics Packaging (ICEP). pp. 9-10. DOI: https://doi.org/10.23919/ICEP51988.2021.9451972

Tags: