A Novel Process for SiGe Core-Shell JAM Transistors Fabrication and Thermal Annealing Effect on Its Electrical Performance

Updata:01-01-1970

Source:
By:Wen-Hsi Lee

DOI: https://doi.org/10.30564/ssid.v1i2.1399

Abstract:
In this study, we fabricate Si/SiGe core-shell Junctionless accumulation
mode (JAM)FinFET devices through a rapid and novel process with four
main steps, i.e. e-beam lithography definition, sputter deposition, alloy
combination annealing, and chemical solution etching. The height of Si
core is 30 nm and the thickness of Si/SiGe core-shell is about 2 nm. After
finishing the fabrication of devices, we widely studied the electrical char
acteristics of poly Si/SiGe core-shell JAM FinFET transistors from a view
of different Lg and Wch. A poly-Si/SiGe core -shell JAMFETs was suc
cessfully demonstrated and it also exhibits a superior subthreshold swing
of 81mV/dec and high on/off ratio > 105 when annealing for 1hr at 600°C.
The thermal diffusion process condition for this study are 1hr at 600°C and
6hr at 700°C for comparison. The annealing condition at 700oC for 6 hours
shows undesired electrical characteristics against the other. Results suggests
that from over thermal budget causes a plenty of Ge to precipitate against
to form SiGe thin film. Annealing JAMFETs at low temperature shows
outstanding Subthreshold swing and better swing condition when com
pared to its counterpart i.e. at higher temperature. This new process can still
fabricate a comparable performance to classical planar FinFET in driving
current.
References:

[1] Xiang, J., et al.. Ge/Si nanowire heterostructures as high-performance field-effect transistors. nature, 2006, 441(7092): 489. [2] Jiang, Y., et al.. Omega-gate p-MOSFET with nanowirelike SiGe/Si core/shell channel. IEEE Electron Device Letters, 2009, 30(4): 392-394. [3] Hashemi, P., et al.. Width-dependent hole mobility in top-down fabricated Si-core/Ge-shell nanowire metal-oxide-semiconductor-field-effect-transistors. Applied Physics Letters, 2010, 96(6): 063109. [4] Woo Lee, J., et al.. Short channel mobility analysis of SiGe nanowire p-type field effect transistors: Origins of the strain induced performance improvement. Applied Physics Letters, 2012, 101(14): 143502. [5] Schmidt, V., et al.. Silicon nanowires: a review on aspects of their growth and their electrical properties. Advanced Materials, 2009, 21(25-26): 2681-2702. [6] David, T., et al.. Tailoring Strain and Morphology of Core–Shell SiGe Nanowires by Low-Temperature Ge Condensation. Nano letters, 2017, 17(12): 7299-7305. [7] Pham, D., L. Larson, J.-W. Yang. FinFET device junction formation challenges. in 2006 International Workshop on Junction Technology. IEEE, 2006. [8] Lee, C.-W., et al.. Junctionless multigate field-effect transistor. Applied Physics Letters, 2009, 94(5): 053511. [9] Lee, C.-W., et al.. Performance estimation of junctionless multigate transistors. Solid-State Electronics, 2010, 54(2): 97-103. [10] Colinge, J.-P., et al.. Nanowire transistors without junctions. Nature nanotechnology, 2010, 5(3): 225. [11] Kim, T.K., et al.. First demonstration of junctionless accumulation-mode bulk FinFETs with robust junction isolation. IEEE Electron Device Letters, 2013, 34(12): 1479-1481. [12] Kranti, A., et al. Junctionless nanowire transistor (JNT): Properties and design guidelines. in 2010 Proceedings of the European Solid State Device Research Conference. IEEE, 2010. [13] Han, M.-H., et al.. Device and circuit performance estimation of junctionless bulk FinFETs. IEEE Transactions on Electron Devices, 2013, 60(6): 1807-1813. [14] Park, C.-H., et al.. Electrical characteristics of 20-nm junctionless Si nanowire transistors. Solid-State Electronics, 2012, 73: 7-10. [15] Leung, G. C.O. Chui, Variability impact of random dopant fluctuation on nanoscale junctionless FinFETs. IEEE Electron Device Letters, 2012, 33(6): 767-769. [16] Rios, R., et al.. Comparison of junctionless and conventional trigate transistors with $ L_ {g} $ down to 26 nm. IEEE electron device letters, 2011, 32(9): 1170-1172. [17] Jeon, D.-Y., et al.. Low-temperature electrical characterization of junctionless transistors. Solid-State Electronics, 2013, 80: 135-141. [18] Hashemi, P., et al.. High-mobility high-Ge-content Si 1− x Ge x-OI PMOS FinFETs with fins formed using 3D germanium condensation with Ge fraction up to x~ 0.7, scaled EOT~ 8.5 Å and ~ 10nm fin width. in 2015 Symposium on VLSI Circuits (VLSI Circuits), IEEE, 2015. [19] Adhikari, H., et al.. High mobility SiGe shell-Si core omega gate pFETS. in 2009 International Symposium on VLSI Technology, Systems, and Applications. IEEE, 2009. [20] Sioncke, S., et al.. Etch rates of Ge, GaAs and InGaAs in acids, bases and peroxide based mixtures. ECS Transactions, 2008, 16(10): 451-460. [21] Huygens, I.M., W.. Gomes, and K. Strubbe, Etching of germanium in hydrogenperoxide solutions. ECS Transactions, 2007, 6(2): 375-386

Tags: